In recent years, an operating voltage of a semiconductor memory device as typified by a DRAM (Dynamic Random Access Memory) has been gradually decreasing so as to reduce power consumption of the semiconductor memory device. Currently, some semiconductor memory devices use quite low operating voltages of about 1 volt. If the operating voltage decreases, it is necessary to reduce a threshold voltage of each transistor accordingly. As a result, a sub-threshold current flowing through the transistor in an off state disadvantageously increases. To solve such a problem, a method of dividing power supply wirings into a main power supply wiring and a pseudo power supply wiring have been proposed in Japanese Patent Application Laid-open Nos. 2000-13215 and 2000-48568.
FIG. 6 is a circuit diagram of a conventional semiconductor memory device using pseudo power supply wirings.
A circuit shown in FIG. 6 includes a circuit block 10 configured to include four stages of inverters 11 to 14. The circuit block 10 is a block the logic of which is fixed in a standby state. In the example shown in FIG. 6, a signal IN input to the circuit block 10 is fixed to high level in the standby state. Needless to say, a logic value of the input signal IN is appropriately changed into an active state.
Four power supply wirings, that is, a main power supply wiring VDD and a pseudo power supply wiring VDT to each of which a power supply potential is supplied, and a main power supply wiring VSS and a pseudo power supply wiring VST to each of which a ground potential is supplied are provided for the circuit shown in FIG. 6. A P-channel MOS transistor 21 is provided between the main power supply wiring VDD and the pseudo power supply wiring VDT, and a standby signal S0B is supplied to a gate electrode of the P-channel MOS transistor 21. Further, an N-channel MOS transistor 22 is provided between the main power supply wiring VSS and the pseudo power supply wiring VST, and a standby signal S0 is supplied to a gate electrode of the N-channel MOS transistor 22. The standby signal S0B is an inverted signal obtained by causing an inverter 23 to invert the standby signal S0.
The standby signal S0 is a signal that becomes low level when the circuit block 10 is set in the standby state, and kept to be high level when the circuit block 10 is in the active state. Due to this, in the active state, the main power supply wiring VDD is shorted to the pseudo power supply wiring VDT via the transistor 21, and the main power supply wiring VST is shorted to the pseudo power supply wiring VSS via the transistor 22. On the other hand, in the standby state, the transistors 21 and 22 are turned into nonconductive states. Due to this, the pseudo power supply wirings VDT and VSS are disconnected from the power supply wirings VDD and VST, respectively. As a result, the power supply potential is hardly supplied to the circuit block 10.
Moreover, among the four inverters 11 to 14 included in the circuit block 10, the first inverter 11 and the third inverter 13 are connected between the pseudo power supply wiring VDT and the main power supply wiring VSS. Further, the second inverter 12 and the fourth inverter 14 are connected between the main power supply wiring VDD and the pseudo power supply wiring VST. As described above, in the active state, the main power supply wiring VDD is shorted to the pseudo power supply wiring VDT, and the main power supply wiring VSS is shorted to the pseudo power supply wiring VST. Accordingly, a power supply voltage is correctly applied to both power supply terminals of each of all the inverters 11 to 14, whereby the circuit block 10 can operate normally. Therefore, a signal OUT output from the circuit bock 10 has a correct value according to the logic value of the input signal IN.
Meanwhile, in the standby state, the pseudo power supply wiring VDT is disconnected from the main power supply wiring VDD, and the pseudo power supply wiring VST is disconnected from the main power supply wiring VSS. Accordingly, the power supply potential is hardly supplied to sources of P-channel MOS transistors 11p and 13p included in the first inverter 11 and the third inverter 13, respectively. In addition, the power supply potential is hardly supplied to sources of N-channel MOS transistors 12n and 14n included in the second inverter 12 and the fourth inverter 14, respectively.
Nevertheless, because the input signal IN is fixed to the high level in the standby state, transistors that are included in the inverters 11 to 14 and that are turned into on states are fixed to an N-channel MOS transistor 11n, a p-channel MOS transistor 12p, an N-channel MOS transistor 13n, and a P-channel MOS transistor 14p shown in FIG. 6, respectively. Furthermore, sources of these transistors 11n, 12p, 13n, and 14p are connected to the main power supply wiring VDD or VSS, so that the logic of the circuit block 10 is maintained correctly in the standby state.
On the other hand, sources of the P-channel MOS transistors 11p and 13p that are turned into off states in the standby state are connected to the pseudo power supply wiring VDT disconnected from the main power supply wiring VDD. Due to this, sub-threshold current hardly flows through the P-channel MOS transistors 11p and 13p. Likewise, sources of the N-channel MOS transistors 12n and 14n that are turned into off states in the standby state are connected to the pseudo power supply wiring VST disconnected from the main power supply wiring VSS. Due to this, sub-threshold current hardly flows through the N-channel MOS transistors 12n and 14n. It is thereby possible to reduce the power consumption while the circuit block 10 is in the standby state.
In this manner, if the power supply wiring is hierarchized by using not only the main power supply wirings, but also the pseudo power supply wirings, the power consumption can be reduced while the circuit block the logic of which is fixed in the standby state is in the standby state.
If such hierarchical power supply wirings are employed in a semiconductor memory device such as a DRAM, it is preferable to apply the hierarchical power supply wirings to an address control circuit block performing access control over a memory cell array and a data I/O circuit block transmitting and receiving data to and from the memory cell array. In this case, it suffices to change each of the address control circuit block and the data I/O circuit block from the standby state into the active state in response to a command signal, e.g., an activation command, issued at the start of a read or write operation.
However, the conventional technique has the following problems. Recent semiconductor memory devices are increasingly becoming multifunctional. Due to this, even in a period in which no read or write operation is carried out, it is often necessary to change a part of circuit blocks into the active state. For example, in a synchronous DRAM of DDR2 type that supports an ODT (On Die Termination) function and an OCD (Off Chip Driver) function, it is necessary to turn a data I/O circuit block into the active state so as to use the ODT or to adjust an OCD impedance.
Due to this, to allow using the ODT or adjusting the OCD impedance while the command, e.g., the activation command, issued at the start of the read or write operation is not issued, it is necessary to constantly turn the data I/O circuit block into the active state, disadvantageously resulting in an increase in power consumption.